Designers of digital circuits rely upon computer aided techniques. Standard hardware description languages (HDLs) such as Verilog, System Verilog, and VHDL have been developed that are used to describe digital circuits. HDLs allow a designer to create a definition of a digital circuit design at the gate level, the register transfer level (RTL), or the behavioral level using abstract data types. A circuit design specified in an HDL may be processed by a computer-aided design tool for implementation as, or within, an integrated circuit.
HDL simulation is a technique for testing the behavior of hardware that is implemented from a circuit design specified in HDL. HDL simulation involves building an executable model of the circuit design originally specified in HDL. The circuit design is often referred to as the “design under test” or “DUT”. The resulting executable version of the circuit design is then executed in combination with an HDL simulator using a data processing system.
In general, HDL simulation includes two phases. The first phase is referred to as compilation. During compilation, the DUT is parsed, elaborated, and executable program code is generated from the DUT. The second phase is a runtime phase where the executable program code generated during compilation is loaded into memory of a data processing system and executed.